A high-speed 2×VDD output buffer with PVTL detection using 40-nm CMOS technology

Author

Chua-Chin Wang ; Tsung-Yi Tsai ; Wei Lin

Author_Institution

Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan

fYear

2015

fDate

1-3 June 2015

Firstpage

1

Lastpage

4

Abstract

Not only PVT detection techniques but also a leakage compensation design are proposed to carry out 650/500 MHz 2×VDD output buffer in this paper. The proposed 2×VDD output buffer contains a novel PVTL (Process, Voltage, Temperature, Leakage) compensation circuit to resolve the problems in output buffers of nano-scale CMOS technologies. Particularly, the leakage compensation design is realized by an asynchronous control method to control current paths such that the switching loss and the slew rate in the output buffer can be reduced and increased, respectively. The proposed design has been realized and implemented by using a typical 40 nm CMOS process. The data rate is 650/500 MHz given 0.9/1.8 V supply voltage with a 20 pF load. The maximum slew rate is 3.5 (V/ns), and the core area is 0.052 × 0.213 mm².

Keywords

CMOS integrated circuits; buffer circuits; compensation; integrated circuit design; CMOS process; PVT detection techniques; PVTL compensation circuit; VDD output buffer; asynchronous control method; current paths; frequency 500 MHz; frequency 650 MHz; leakage compensation design; nano-scale CMOS technologies; output buffers; size 40 nm; switching loss; voltage 0.9 V; voltage 1.8 V; CMOS integrated circuits; CMOS technology; Detectors; Inverters; Leakage currents; Logic circuits; I/O buffer; PVTL variation; gate-oxide reliability; mixed-voltage tolerant; slew rate compensation;

fLanguage

English

Publisher

ieee

Conference_Titel

IC Design & Technology (ICICDT), 2015 International Conference on

Conference_Location

Leuven

Type

conf

DOI

10.1109/ICICDT.2015.7165914

Filename

7165914