DocumentCode
726293
Title
ProPRAM: Exploiting the transparent logic resources in Non-Volatile Memory for Near Data Computing
Author
Ying Wang ; Yinhe Han ; Lei Zhang ; Huawei Li ; Xiaowei Li
Author_Institution
State Key Lab. of Comput. Archit., Inst. of Comput. Technol., Beijing, China
fYear
2015
fDate
8-12 June 2015
Firstpage
1
Lastpage
6
Abstract
Emerging highly-parallel and big data applications have renewed the research interest in Processing-in-Memory (PIM) architectures. However, moving powerful processing unit into the CMOS-incompatible DRAM chips is not cost-effective for large capacity memory. In this work, we observe that Non-Volatile Memory is often naturally incorporated with basic logics like Data Comparison Write or Flip-n-Write modules that are essential for cell SET/REST operation. In contrast to other conventional PIM or Near Data Computing (NDC) architectures, ProPRAM, as a typical Active NVM, abandons the design approach of moving accelerators or customized processors into memory devices, but begins with exploiting the existing resources inside the memory chips to accelerate the key non-compute-intensive functions for emerging big data applications. With slight hardware and architectural modification, we succeed to expose the transparent peripheral logics to the application layer through instruction set extension and exploit them for in-field bulk data processing with limited hardware cost. Compared to conventional CPU-centric systems, ProPRAM achieves an excellent optimization on energy-efficiency (15×) for important data-intensive micro-benchmarks and kernels.
Keywords
Big Data; CMOS integrated circuits; DRAM chips; parallel architectures; random-access storage; CMOS; CPU-centric systems; NDC architecture; NVM; PIM architecture; ProPRAM; architectural modification; big data application; cell SET-REST operation; comparison write data module; flip-n-write module; incompatible DRAM chips; instruction set extension; memory chips; memory devices; near data computing architecture; non-compute-intensive functions; nonvolatile memory; optimization; processing-in-memory architecture; transparent logic resource; transparent peripheral logics; Assembly; Clustering algorithms; DRAM chips; Performance evaluation; Radar; Redundancy;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference (DAC), 2015 52nd ACM/EDAC/IEEE
Conference_Location
San Francisco, CA
Type
conf
DOI
10.1145/2744769.2744897
Filename
7167203
Link To Document