Routing-architecture-aware analytical placement for heterogeneous FPGAs

Placement is a crucial stage for FPGA implementation. Most FPGA placers optimize their placement results by minimizing half-perimeter wirelength (HPWL). Due to the segmented routing architecture in FPGAs, however, the HPWL function cannot model routed wirelength and delay well. The mismatch of the HPWL function might lead to inferior routing results. Further, heterogeneous circuit blocks in a modern FPGA make the placement problem more complex. Consequently, it is desirable to consider the segmented routing and heterogeneous circuit architecture for FPGA placement. This paper presents a routing-architecture-aware analytical placement algorithm for heterogeneous FPGAs. Our algorithm proposes a routing-architecture-aware cost function to make placement results adapt to the corresponding routing architecture, and a complex block density model to effectively handle the heterogeneity. Experimental results show that our placer can achieve 9% smaller critical path delay and 5% shorter routed wirelength with shorter runtime, compared to the state-of-the-art academic placer.