Design for low test pattern counts

Author

Konuk, Haluk ; Moghaddam, Elham ; Mukherjee, Nilanjan ; Rajski, Janusz ; Solanki, Deepak ; Tyszer, Jerzy ; Zawada, Justyna

Author_Institution

Broadcom Corp., Irvine, CA, USA

fYear

2015

fDate

8-12 June 2015

Firstpage

1

Lastpage

6

Abstract

This paper presents a new method to design digital circuits for low pattern counts, one of the key factors shaping cost-effective VLSI test schemes. The method identifies the largest conflicts between internal signals that prevent efficient test compaction in ATPG. These locations are modified by inserting conflict-reducing test points (CRTP) to significantly reduce the ATPG-produced pattern counts. Experimental results obtained for large industrial designs with on-chip test compression demonstrate, on average, 3x - 4x reduction in stuck-at and transition patterns and 3x shorter ATPG times.

Keywords

automatic test pattern generation; integrated circuit testing; ATPG; automatic test pattern generation; conflict reducing test points; cost effective VLSI test; digital circuit design; low pattern count circuit design; low test pattern counts; test compaction; Automatic test pattern generation; Circuit faults; Clocks; Computer architecture; Integrated circuit modeling; Logic gates; Design for testability; scan-based test; test data compression;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference (DAC), 2015 52nd ACM/EDAC/IEEE

Conference_Location

San Francisco, CA

Type

conf

DOI

10.1145/2744769.2744817

Filename

7167321