DocumentCode
726416
Title
SoC security architecture: Current practices and emerging needs
Author
Peeters, Eric
Author_Institution
Texas Instrum. Inc., Dallas, TX, USA
fYear
2015
fDate
8-12 June 2015
Firstpage
1
Lastpage
6
Abstract
At the era of everything is connected, security has become an essential key question when starting a new System-on-chip architecture. With the proliferation of secure systems, it is expected that many design teams will lack the essential knowledge and time to look at the abundant literature. In this paper, we intend to provide a reasonable approach to tackle this problem and try to convey the essential design rules, design elements and threats to any reader. We cover a possible methodology to collect requirements based on a systematic identification of the assets needing protection and threats against these assets: and make sure the design is appropriately sized and adequately secure. Once the requirements have been collected, the architecture can be laid out and we discuss the main elements that can compose it: trusted execution environment, secure boot, secure software update, secure design-for-test (DFT) components, Random Number Generation (RNG).
Keywords
integrated circuit design; security of data; system-on-chip; DFT components; RNG; SoC security architecture; design elements; design rules; random number generation; secure boot; secure design-for-test components; secure software update; system-on-chip architecture; systematic identification; trusted execution environment; Computer architecture; Computer hacking; Cryptography; Random access memory; Software; System-on-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference (DAC), 2015 52nd ACM/EDAC/IEEE
Conference_Location
San Francisco, CA
Type
conf
DOI
10.1145/2744769.2747943
Filename
7167330
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