Automated selection of check variables for area-efficient soft-error tolerant datapath synthesis

As the size of semiconductor devices has decreased, reliability degradation caused by soft-errors has become one of the greatest issues in VLSI circuit design. In this paper, we propose a method to synthesize soft-error tolerant application-specific datapaths via high-level synthesis. Our method is based on a concurrent error detection and a retry mechanism for error detection and error correction. The proposed model makes two novel contributions: (1) speculative resource sharing between retry parts and secondary parts for hardware/time overhead mitigation; (2) selective insertion of comparison-operations which detects soft-errors in order to increase the opportunity for speculative resource sharing. Datapath synthesis experiments found that the combination of speculative resource sharing and the selective insertion of comparison-operations achieves a maximum 32.3% improvement in latency.