3D vertical RRAM architecture and operation algorithms with effective IR-drop suppressing and anti-disturbance

We propose co-optimization of VRRAM cell structure and array architecture as well as IR-drop-aware read/write algorithms to overcome issues of disturbance and IR drop from long wire. A bi-directional diode (2D) access device is combined with one resistor to form 2D1R cell. A dummy reference plane is inserted into array to set up the same IR drop path of reference cell with that of selected cell. Consequently, the same IR drop effect can be cancelled during read. The model for disturbance analysis is put forward. Voltage dropped on un-selected bit lines is the key parameter to suppress set disturbance. Set disturbance is significantly suppressed even when number of RRAM layers increases to 64. Set voltage has to meet corresponding requirements in order to minimize the disturbance risk.