DocumentCode :
727051
Title :
Partial sums computation in polar codes decoding
Author :
Berhault, Guillaume ; Leroux, Camille ; Jego, Christophe ; Dallet, Dominique
Author_Institution :
IMS Res. Lab., Univ. of Bordeaux, Talence, France
fYear :
2015
fDate :
24-27 May 2015
Firstpage :
826
Lastpage :
829
Abstract :
Polar codes are the first error-correcting codes to provably achieve the channel capacity but with infinite code-lengths. For finite code lengths the existing decoder architectures are limited in working frequency by the partial sums computation unit. We explain in this paper how the partial sums computation can be seen as a matrix multiplication. Then, an efficient hardware implementation of this product is investigated. It has reduced logic resources and interconnections. Formalized architectures, to compute partial sums and to generate the bits of the generator matrix κ⊗n, are presented. The proposed architecture allows removing the multiplexing resources used to assigned to each processing elements the required partial sums.
Keywords :
decoding; error correction codes; matrix algebra; channel capacity; decoder architectures; first error correcting codes; formalized architectures; generator matrix; infinite code lengths; matrix multiplication; partial sums computation unit; polar codes decoding; Computer architecture; Decoding; Error correction codes; Hardware; Indexes; Multiplexing; Signal processing; FEC; hardware architecture; polar codes; successive cancellation decoding;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (ISCAS), 2015 IEEE International Symposium on
Conference_Location :
Lisbon
Type :
conf
DOI :
10.1109/ISCAS.2015.7168761
Filename :
7168761
Link To Document :
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