DocumentCode :
727102
Title :
17-MS/s 9-bit cyclic ADC with gain-assisted MDAC and attenuation-based calibration
Author :
Okada, Yuki ; Oshima, Takashi
Author_Institution :
Central Res. Lab., Hitachi, Ltd., Tokyo, Japan
fYear :
2015
fDate :
24-27 May 2015
Firstpage :
1254
Lastpage :
1257
Abstract :
A 17-MS/s 52.5-dB-SNDR 4.7-mW 0.045-mm2 cyclic ADC has been achieved by the low-cost 0.18-μm CMOS. The only-26-dB gain of a simple op-amp has been successfully compensated by the proposed gain-assisted MDAC circuit and by the novel simple attenuation-based digital calibration. The prototype ADC chip has achieved the fastest speed, the smallest size and the best FOM among the high-speed (> 5 MS/s) highresolution (SNDR > 50 dB) low-cost-CMOS cyclic ADCs.
Keywords :
analogue-digital conversion; calibration; low-power electronics; operational amplifiers; attenuation-based calibration; digital calibration; gain 26 dB; gain-assisted MDAC circuit; low-cost-CMOS cyclic ADC; multiplying analog-to-digital converter; power 4.7 mW; simple attenuation; simple op-amp; size 0.18 mum; word length 9 bit; Attenuation; Attenuation measurement; CMOS integrated circuits; Calibration; Frequency measurement; Power measurement; Prototypes; MDAC; cyclic ADC; digital calibration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (ISCAS), 2015 IEEE International Symposium on
Conference_Location :
Lisbon
Type :
conf
DOI :
10.1109/ISCAS.2015.7168868
Filename :
7168868
Link To Document :
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