Fine-grain DVFS and AVFS techniques for complex SoC design: An overview of architectural solutions through technology nodes

In this paper we propose to give an overview of fine-grain design techniques we demontrated past years in our lab for power reduction in complex SoCs. Those works are based on Globally Asynchronous and Locally Synchronous systems in which each IP is an independent voltage and frequency domain. After having proposed some simple DFS architectures based on GALS architectures in 130nm technology, we extended our works to fine-grain Dynamic Voltage and Frequency Scaling architectures to reduce dynamic and static power reduction at 65 nm node. Furthermore, considering 32 nm deep submicron technologies, we demonstrated an Adaptive Voltage and Frequency architecture to compensate for in-die PVT variations. Area overhead and power reduction results are discussed all along the paper.