On the reuse of existing error tolerance circuitry for low power scan testing

Timing errors are a major threat in nanometer technology integrated circuits. Razor is a well known timing error tolerance design technique. However, its silicon area cost makes it unattractive for widespread use. In this work, we reuse the Razor topology in order to achieve low power scan testing operations and make this technique a viable solution which will serve both on-line and off-line testing requirements. In addition, the ability to apply this technique for at-speed scan testing is also explored in this work. According to the experimental results, the scan power consumption is drastically reduced since the signal transitions at the inputs of the combinational logic are eliminated during the scan testing operations.