Selectable starting bit SAR ADC

Prior work used least-significant bit first quantization (LSBFQ) to conserve switching energy and comparator bitcycles, but is limited to low activity signals. Furthermore, LSBFQ results in a large bitcycle range in the quantizer. A novel selectable starting bit quantizer (SSBQ) is proposed which starts quantization with neither the MSB nor the LSB, but an intermediate bit chosen for target applications. It is shown that the proposed algorithm reduces bitcycle range in the quantizer compared to LSBFQ, and provides design flexibility for various activity signals. Furthermore, the proposed solution encompasses LSBFQ since it is a specific case of the proposed architecture. For target applications, the proposed solution will save bitcycles in an A/D conversion, as well as switching energy, over the LSBFQ and the merged capacitor switching (MCS) SAR, the most energy-efficient traditional MSB-first SAR.