An injection-locked oscillator-multiplier circuitry suitable for MB-OFDM clock generation

A circuit architecture capable of generating fast-hopping multiple local oscillator signals is presented. It is based on first harmonic injection-locked ring-oscillator, which extracts the Nth harmonic from an N-stage injection-locked oscillator. To study this technique, a multiply-by-nine with nine-stage single-ended ring-oscillator has been fabricated using 350nm CMOS technology. The free-running frequency of the oscillator is 1.05 GHz with a phase-noise of -71 dBm/dBc at the 1 MHz offset frequency. The locked phase-noise is -116 dBm/dBc. The circuit draws 6 mA from a 1.5 V supply. Further, based on the proposed circuit, the clock architecture suitable for MB-OFDM has been simulated using 65 nm CMOS technology.