A 12A 50V half-bridge gate driver for enhancement-mode GaN HEMTs with digital dead-time correction

This paper presents a high-frequency half-bridge driver for enhancement-mode GaN-on-Si HEMTs with digital dead-time correction (DDTC) to optimize the dead-time. Due to the lateral HEMT structure, dead-time optimization is essential for synchronous driving. It helps reducing the reverse conduction loss to enhance the efficiency and reliability. The DDTC scheme achieves instant sensing with all-digital feedback control to adjust the dead-times dynamically according to load changes. The proposed half-bridge driver for GaN HEMTs is designed in 0.35μm HV CMOS technology. Simulation results show that the DDTC scheme is able to reduce the dead-times to within 2ns and the efficiency is improved by 4.9% compared to the fixed dead-time scheme in a 12V-1.2V conversion with a 12A load current.