Memory-efficient discrete wavelet transform architecture based on wordlength optimization

Unlike the existing designs that improve the memory efficiency by reducing the on-chip memory words, we propose a memory-efficient 2-D DWT architecture which improves the memory efficiency by reducing the wordlength of the on-chip memory. Based on our recently proposed memory-efficient 2-D DWT architecture, which achieves the highest memory efficiency among the existing designs, we analyze the dynamic range and optimize the required integer bit (IB) width of every internal signal for memory reduction. We construct an architecture-specific accuracy model for both 9/7 and 5/3 2-D DWT and optimize the factional bit (FB) width of every internal signal without sacrificing the precision of the output. Theoretical estimation shows a 17.5% reduction of the temporal memory regardless of input image size and throughput. In addition, the arithmetic resource is reduced. The synthesis results in 90-nm CMOS show a better area-delay product (ADP) of 25.1% over the best existing design.