Live demonstration: Efficient event-driven approach using synchrony processing for hardware spiking neural networks

Recent neuromorphic applications now use spiking neural networks (SNNs) because of their improved computational power compared to previous generations of neural networks. Efficient simulation is essential when using this type of neuron since many events have to be handled on a large number of neurons within the network. In this demonstration, a hardware simulator for SNNs that has applications in image recognition is presented. This SNN uses synchrony processing for efficient event-driven simulation (SPEEDS) which allows parallel computations of synchronized events. SPEEDS differs from common event-driven approaches that serialize every event and can improve significantly the computational efficiency of a SNN simulator. The hardware SNN is implemented on a Xilinx Virtex-6 XC6VLX240T field-programmable gate array (FPGA) and can contain 131 072 neurons. It can process approximately 70 million spikes per second on a 4-bank architecture clocked at 100 MHz. The presentation explains how such a system can be used for image processing tasks like image segmentation, feature extraction and pattern matching to realize a recognition system that can detect several objects in a given image.