DLL based test solution for interposers in 2.5-D ICs

Author

Mashkovtsev, V. ; Attaran, A. ; Rashidzadeh, R.

Author_Institution

Electr. & Comput. Eng., Univ. of Windsor, Windsor, ON, Canada

fYear

2015

fDate

24-27 May 2015

Firstpage

2261

Lastpage

2264

Abstract

Silicon interposer is the enabling technology for 2.5D IC integration which supports higher levels of integration and improved electrical performance. An interposer can suffer from various physical defects affecting the overall performance of 2.5D ICs. This paper presents a new method to perform manufacturing tests for interposers utilizing a Delay Locked Loop (DLL). In the proposed method short-time intervals are first amplified through a time-amplifier and then measured. Simulation results using ADS software with 65 nm TSMC CMOS technology indicates that proposed method can detect minor structural defects affecting the propagation delay of interconnect by more than 1.5ps resolution.

Keywords

CMOS integrated circuits; delay lock loops; elemental semiconductors; integrated circuit interconnections; silicon; three-dimensional integrated circuits; 2.5D IC integration; ADS software; DLL; Si; TSMC CMOS technology; delay locked loop; propagation delay; silicon interposer; size 65 nm; time-amplifier; Circuit faults; Delays; Integrated circuit interconnections; Integrated circuit modeling; Propagation delay; Silicon; Solid modeling; 2.5D IC integration; Delay locked loop (DLL); Design-for-test; parametric faults; test for interposers;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), 2015 IEEE International Symposium on

Conference_Location

Lisbon

Type

conf

DOI

10.1109/ISCAS.2015.7169133

Filename

7169133