Unified approach for simulation of statistical reliability in nanoscale CMOS transistors from devices to circuits

In this paper we will present integrated time dependent variability tool flow that links statistical TCAD simulations, statistical compact model extraction and statistical circuit simulation. This allows the concepts of Design-Technology Co-Optimization (DTCO) to be extended into the reliability domain. The simulations are based on Gold Standard Simulations´ (GSS) 3-D Kinetic Monte Carlo TCAD technology, which enables the simulation and analysis of the trapping/de-trapping history of large ensembles of microscopically different transistors. The results of the physical simulation are than captured in accurate time dependent statistical compact models. As a result, accurate statistical circuit simulation can trace the statistical impact of the degradation on the functionality of the underlying circuits and systems.