A 400 mV atrial fibrillation detector with 0.56 pJ/operation in 65nm CMOS

A real-time atrial fibrillation (AF) detector that detects episodes with statistical methods is fabricated in a 65nm high-V_T CMOS process. Detection sensitivity of 94.9 % and specificity of 95.8 % are achieved for the commonly used MIT-BIH AF database. The architecture is optimized for clock- and power-gating. The design of full-custom power switches limits the power-gating area overhead to 6%. The core energy dissipation at the energy minimum point is 0.56 pJ/operation using powergates at a supply voltage of 0.4V. Targeting a medical implant operation at 37°C results in a speed increase of 1.5X at a cost of 22% higher energy dissipation. Correct operation is observed down to 0.29V. A core energy reduction of 71% was attained with power-gating.