A low-voltage, low-power amplifier created by reasoning-based, systematic topology synthesis

This paper introduces a three stage low voltage, low power amplifier created by a design knowledge-intensive circuit topology synthesis methodology. The synthesis method flow begins with a set of starting ideas and then continues with a sequence of justified, causal design steps. Starting ideas combine physical and abstract features from either previous design or new insight. After combining the starting ideas, the related design sequence is identified step by step, so that each step either improves performance or relaxes design constraints. The created Opamp is a novel low voltage, low power circuit with better setting time (small signal characteristic) and slew rate (large signal characteristic). The proposed Opamp is realized in 0.2-μm CMOS technology. At 1-V supply voltage, it consumes less than 70μW static power. When driving a 5-pF capacitive load, the amplifier achieves 24MHz gain-bandwidth-product (GBW) and 5.1-V/μs average slew rate.