Title :
Subblock-level matching layout for analog block-pair and its manufacturability evaluation
Author :
Hirata, Takuya ; Nishino, Ryuta ; Nakatake, Shigetoshi ; Shimoyama, Masaya ; Miyagawa, Masashi ; Tanno, Koichi ; Yamada, Akihiro
Author_Institution :
Univ. of Kitakyushu, Kitakyushu, Japan
Abstract :
This paper presents a layout-dependent manufacturability for analog integrated circuits. We focus on the relative variability of input op-amp-pair used in an instrumentation amplifier (in-amp). We propose a subblock-level matching layout style such that subblocks of the op-amp-pair are superimposed aiming to suppress the relative variability dependent on the layout. We fabricate chips according to five superposed layout styles and evaluate the relative variability in terms of the DC offset, so that we demonstrate the most effective layout style. Besides, we provide a manufacturability simulation methodology to evaluate the in-amp considering the relative variability of the op-amp-pair based on the measurement results. Comparing the simulation result and the performances of fabricated in-amps, we are convinced our methodology can evaluate the layout-dependency of the manufacturability by the simulation.
Keywords :
analogue integrated circuits; instrumentation amplifiers; integrated circuit manufacture; operational amplifiers; DC offset; analog block-pair; analog integrated circuit; in-amp; instrumentation amplifier; layout-dependent manufacturability; manufacturability evaluation; manufacturability simulation methodology; op-amp-pair; relative variability; subblock-level matching layout; Accuracy; Monte Carlo methods; analog layout; instrumentation amplifier; layout-dependent manufacturability; matching layout;
Conference_Titel :
Circuits and Systems (ISCAS), 2015 IEEE International Symposium on
Conference_Location :
Lisbon
DOI :
10.1109/ISCAS.2015.7169321