PADI, an Ultrafast Preamplifier - Discriminator ASIC for Time-of-Flight Measurements

Author

Ciobanu, M. ; Herrmann, N. ; Hildenbrand, K.D. ; Kis, M. ; Schuttauf, A. ; Flemming, H. ; Deppe, H. ; Lochner, S. ; Fruhauf, J. ; Deppner, I. ; Loizeau, P.A. ; Trager, M.

Author_Institution

GSI Helmholtzzentrum, Darmstadt, Germany

Volume

61

Issue

2

fYear

2014

fDate

Apr-14

Firstpage

1015

Lastpage

1023

Abstract

The design of a general-purpose PreAmplifier-DIscriminator ASIC chip, PADI, is presented in this article. PADI is intended to be used as Front-End-Electronics (FEE) for reading out the timing Resistive-Plate Chambers (RPCs) in the time-of-flight (ToF) wall of the CBM detector for the future FAIR facility in Darmstadt-Germany, which will comprise about 100,000 channels in a 150 m² area. The evolution of this 0.18 μm CMOS technology design will be presented, from the first prototype PADI-1 to the last one, PADI-8, as well as its features and test results.

Keywords

CMOS integrated circuits; application specific integrated circuits; discriminators; nuclear electronics; position sensitive particle detectors; preamplifiers; readout electronics; CBM detector; CMOS technology design; Darmstadt; Germany; PADI-8; front-end-electronics; future FAIR facility; prototype PADI-1; time-of-flight measurements; time-of-flight wall; timing resistive-plate chambers; ultrafast PreAmplifier-DIscriminator ASIC chip PADI; Application specific integrated circuits; Detectors; Impedance; Mirrors; Resistors; Semiconductor device measurement; Signal resolution; ASIC; Analog-digital integrated circuit; CMOS; timing circuits;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/TNS.2014.2305999

Filename

6786378