Smart I/Os: a data-pattern aware 2.5D interconnect with space-time multiplexing

Author

Manoj, Sai ; Kanwen Wang ; Hantao Huang ; Hao Yu

Author_Institution

Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore, Singapore

fYear

2015

fDate

6-6 June 2015

Firstpage

1

Lastpage

6

Abstract

A data-pattern aware smart I/O is introduced in this paper for 2.5D through-silicon interposer (TSI) interconnect based memory-logic integration. To match huge many-core bandwidth demand with limited supply of 2.5D I/O channels when accessing one shared memory, a space-time multiplexing based channel utilisation is developed inside the memory controller to reuse 2.5D I/O channels. Many cores are adaptively classified into clusters based on the bandwidth demand by space multiplexing to access the shared memory. Time multiplexing is then performed to schedule the cores in one cluster to occupy the supplied 2.5D I/O channels at different time-slots upon priority. The proposed smart 2.5D TSI I/O is verified by the system-level simulator with benchmarked workloads, which shows up to 58.85% bandwidth balancing and 11.90% QoS improvement.

Keywords

integrated circuit design; integrated circuit interconnections; multiplexing; three-dimensional integrated circuits; QoS improvement; bandwidth balancing; data pattern aware 2.5D interconnect; many core bandwidth demand; memory-logic integration; shared memory access; smart input-output; space multiplexing; space time multiplexing; through silicon interposer interconnect; Bandwidth; Benchmark testing; Memory management; Microprocessors; Multiplexing; Quality of service; Resource management;

fLanguage

English

Publisher

ieee

Conference_Titel

System Level Interconnect Prediction (SLIP), 2015 ACM/IEEE International Workshop on

Conference_Location

San Francisco, CA

Type

conf

DOI

10.1109/SLIP.2015.7171707

Filename

7171707