Stacked low-voltage PMOS for high-voltage ESD protection with latchup-free immunity

Author

Kai-Neng Tang ; Seian-Feng Liao ; Ming-Dou Ker ; Hwa-Chyi Chiou ; Yeh-Jen Huang ; Chun-Chien Tsai ; Yeh-Ning Jou ; Geeng-Lih Lin

Author_Institution

Inst. of Electron., Nat. Chiao-Tung Univ., Hsinchu, Taiwan

fYear

2015

fDate

26-29 May 2015

Firstpage

325

Lastpage

328

Abstract

Electrostatic discharge (ESD) and latchup are important reliability issues to the CMOS integrated circuits in high-voltage (HV) applications. In this work, the stacked low-voltage (LV) PMOS has been verified to sustain a high ESD level with high holding voltage in a 0.25-μm BCD process. Stacked devices in different configuration were also investigated in silicon chip to get high ESD robustness and latchup-free immunity for HV applications.

Keywords

CMOS integrated circuits; MOS integrated circuits; electrostatic discharge; BCD process; CMOS integrated circuits; LV PMOS; electrostatic discharge; high voltage ESD protection; latchup free immunity; stacked devices; stacked low voltage PMOS; Clamps; Electrostatic discharges; Robustness; Silicides; Stacking; Stress; Voltage measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Electromagnetic Compatibility (APEMC), 2015 Asia-Pacific Symposium on

Conference_Location

Taipei

Print_ISBN

978-1-4799-6668-4

Type

conf

DOI

10.1109/APEMC.2015.7175270

Filename

7175270

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=729062