Architecture for single iteration reconstruction algorithm

Author

Draganic, Andjela ; Orovic, Irena ; Lekic, Nedjeljko ; Dakovic, Milos ; Stankovic, Srdjan

Author_Institution

Fac. of Electr. Eng., Univ. of Montenegro, Podgorica, Montenegro

fYear

2015

fDate

14-18 June 2015

Firstpage

77

Lastpage

80

Abstract

A hardware architecture for the single iteration algorithm is proposed in this paper. Single iteration algorithm enables reconstruction of the full signal when small number of signal samples is available. The algorithm is based on the threshold calculation, and allows distinguishing between signal components and noise that appears as a consequence of missing samples. The proposed system for hardware realization is divided into three parts, each part with different functionality. The system is suitable for the FPGA realization. Realization of the blocks for which there are no standard components in FPGA, is discussed as well.

Keywords

field programmable gate arrays; iterative methods; signal reconstruction; signal sampling; FPGA realization; hardware architecture; signal reconstruction; signal samples; single iteration reconstruction algorithm; threshold calculation; Compressed sensing; Computer architecture; Discrete Fourier transforms; Field programmable gate arrays; Hardware; Noise; Signal processing algorithms; Compressive Sensing; FPGA; hardware; single iteration reconstruction algorithm; sparsity;

fLanguage

English

Publisher

ieee

Conference_Titel

Embedded Computing (MECO), 2015 4th Mediterranean Conference on

Conference_Location

Budva

Print_ISBN

978-1-4799-8999-7

Type

conf

DOI

10.1109/MECO.2015.7181870

Filename

7181870