DocumentCode :
732173
Title :
Design and high-performance hardware architecture for image coding using block-lifting-based quaternionic paraunitary filter banks
Author :
Petrovsky, Nick A. ; Stankevich, Andrew V. ; Petrovsky, Alexander A.
Author_Institution :
Dept. of Comput. Eng., Belarusian State Univ. of Inf. & Radioelectron., Minsk, Belarus
fYear :
2015
fDate :
14-18 June 2015
Firstpage :
193
Lastpage :
198
Abstract :
In this paper, we have introduced a generalized block-lifting structure using the 2-D CORDIC algorithm as a block of 4-band linear phase paraunitary filter banks (LP PUFB) based on the quaternionic algebra (Q-PUFB) for the lossy-to-lossless image coding. A bank Q-PUFB based on the 2-D CORDIC block-lifting structure reduces the number of rounding operations and has a regular layout. Since the block-lifting structures with rounding operations can implement the integer-to-integer transform (Q-PUFB). The parallel-pipelined efficient architecture (P2E_Q-PUFB) has been proposed. The low latency separable image processing is implemented in the given architecture.
Keywords :
algebra; channel bank filters; digital arithmetic; image coding; 2D CORDIC algorithm; 4-band linear phase paraunitary filter banks; LP PUFB; Q-PUFB; generalized block-lifting structure; high-performance hardware architecture; lossy-to-lossless image coding; quaternionic algebra; quaternionic paraunitary filter banks; Computational efficiency; Decision support systems; Embedded computing; Filter banks; Handheld computers; Image coding; Transforms;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Embedded Computing (MECO), 2015 4th Mediterranean Conference on
Conference_Location :
Budva
Print_ISBN :
978-1-4799-8999-7
Type :
conf
DOI :
10.1109/MECO.2015.7181901
Filename :
7181901
Link To Document :
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