Q-enhancement with on-chip inductor optimization for reconfigurable Δ-Σ radio-frequency ADC

Author

Lota, Jaswinder ; Demosthenous, Andreas

Author_Institution

Sch. of Archit., Comput. & Eng., Univ. of East London, London, UK

fYear

2015

fDate

7-10 June 2015

Firstpage

1

Lastpage

4

Abstract

The paper details on-chip inductor optimization for a reconfigurable continuous-time delta-sigma (Δ-Σ) modulator based radio-frequency analog-to-digital converter. Inductor optimisation enables the Δ-Σ modulator with Q enhanced LC tank circuits employing a single high Q-factor on-chip inductor and lesser quantizer levels thereby reducing the circuit complexity for excess loop delay, power dissipation and dynamic element matching. System level simulations indicate at a Q-factor of 75 Δ-Σ modulator with a 3-level quantizer achieves dynamic ranges of 106, 82 dB and 84 dB for RFID, TETRA, and Galileo over bandwidths of 200 kHz, 10 MHz and 40 MHz respectively.

Keywords

LC circuits; Q-factor; analogue-digital conversion; circuit optimisation; continuous time systems; delta-sigma modulation; inductors; logic design; reconfigurable architectures; synchronisation; Galileo; LC tank circuit; Q-enhancement; Q-factor on-chip inductor; RFID; TETRA; circuit complexity; dynamic element matching; frequency 10 MHz; frequency 200 kHz; frequency 40 MHz; loop delay; on-chip inductor optimization; power dissipation; radio-frequency analog-to-digital converter; reconfigurable Δ-Σ radio-frequency ADC; reconfigurable continuous-time Δ-Σ modulator; reconfigurable continuous-time delta-sigma modulato; three-level quantizer; Frequency modulation; Inductors; Q-factor; Radio frequency; Radiofrequency identification; System-on-chip; Q-enhancement; RF delta-sigma; on-chip inductor;

fLanguage

English

Publisher

ieee

Conference_Titel

New Circuits and Systems Conference (NEWCAS), 2015 IEEE 13th International

Conference_Location

Grenoble

Type

conf

DOI

10.1109/NEWCAS.2015.7182018

Filename

7182018