Enhancing a HEVC interpolation filter hardware architecture with efficient adder compressors

The recent High Efficient Video Coding (HEVC) standard introduces a new and complex interpolation filter for fractional-pixel motion estimation. Recent works propose hardware architectures to accelerate the interpolation filter, employing interpolation datapaths with many adders in parallel. Adder compressors are area- and power-efficient operators that are applied when intermediate additions are not required, which is the case for interpolation filters. This work employs various hierarchical adder compressor structures in the interpolation filter datapaths of a state-of-the-art HEVC interpolation filter architecture. Hardware design results show that datapaths using adder compressors reduce power by up to 15% and power delay product by up to 30% compared to the same filters with ripple-carry adders.