Power-efficient hardware architecture for computing Split-Radix FFTs on highly sparsed spectrum

A power efficient hardware architecture implementing the Split-Radix Fast Fourier Transform (SRFFT) is developed through pruning unnecessary computations. SRFFT is known to offer a performance that is better than conventional FFT in terms of reduced number of required complex multiplications and hence, can lead to reduced power consumption. Leveraging this potential, a new architecture of a configurable SRFFT processor is first devised and then the architecture is developed further so that unnecessary computations, which yield zeros at the output, are pruned. This is done through stalling butterfly computations with appropriate use of a pruning matrix. The proposed processor may find applications in orthogonal frequency division multiplexing (OFDM) communication transceivers, where transmitted signals may occupy only a small portion of the whole operational spectrum. The processor is implemented on a field-programmable gate array and simulations show that maximum power saving of around 20% is achieved when computing 1024 point Fourier transform of signals with very sparse spectrum.