SPICE-Based Performance Analysis of Trigate Silicon Nanowire CMOS Circuits

Author

Tanaka, C. ; Saitoh, Masatoshi ; Ota, Kaoru ; Uchida, Kazunori ; Numata, T.

Author_Institution

Adv. LSI Technol. Lab., Toshiba Corp., Yokohama, Japan

Volume

60

Issue

4

fYear

2013

fDate

Apr-13

Firstpage

1451

Lastpage

1456

Abstract

An ultralow-voltage performance is investigated in nanowire transistors (NW Tr.) CMOS circuits. SPICE model parameters of BSIM4 are extracted from measurement data of NW Tr. fabricated on 300-mm SOI wafer. The delay time and the power consumption are examined between nanowire and bulk-Si CMOS circuits. The operation voltage of a nanowire CMOS inverter with an ideal subthreshold slope can be reduced by 300 mV from that of the bulk-Si CMOS inverter. NW-Tr.-based circuits under voltage scaling have immunity from supplying voltage fluctuation and suppression of operation delay variation.

Keywords

CMOS integrated circuits; SPICE; elemental semiconductors; invertors; low-power electronics; nanowires; silicon; silicon-on-insulator; BSIM4; CMOS circuits; SOI wafer; SPICE based performance analysis; delay time; nanowire CMOS inverter; nanowire transistors; power consumption; size 300 nm; subthreshold slope; trigate silicon nanowire; ultralow-voltage performance; voltage 300 mV; voltage fluctuation; voltage scaling; CMOS integrated circuits; Delays; Inverters; Logic gates; Power demand; SPICE; Semiconductor device modeling; CMOS circuit; SPICE parameter; low power; nanowire transistor; parameter extraction;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2013.2247607

Filename

6471797