A 1.2–5Gb/s 1.4–2pJ/b serial link in 22nm CMOS with a direct data-sequencing blind oversampling CDR

Author

Shekhar, Sudip ; Inti, Rajesh ; Jaussi, James ; Tzu-Chien Hsueh ; Casper, Bryan

Author_Institution

Univ. of British Columbia, Vancouver, BC, Canada

fYear

2015

fDate

17-19 June 2015

Abstract

A scalable-rate serial link - comprising of a bidirectional transmitter (TX)/receiver (RX) and two all-digital PLLs (ADPLLs) - operates at 1.2-5Gb/s from 0.55-0.7V DC supply with 1.4-2pJ/b total energy efficiency, respectively. Power efficiency is improved by avoiding the use of any analog circuitry, a low swing voltage-mode transmitter, and a direct data-sequencing blind oversampling (DDS-BOS) clock and data recovery (CDR). Using DDS in feed-forward BOS-CDR obviates area and power consuming FIFOs, improves jitter tolerance (JTOL), and permits up to 7500ppm frequency tolerance (FTOL) between the TX-RX clocks - rendering it attractive for fast-locking continuous/burst operation.

Keywords

CMOS digital integrated circuits; clock and data recovery circuits; jitter; phase locked loops; CMOS; all-digital PLL; analog circuitry; bidirectional transmitter/receiver; clock and data recovery; direct data-sequencing blind oversampling CDR; frequency tolerance; jitter tolerance; low swing voltage-mode transmitter; power efficiency; scalable-rate serial link; voltage 0.55 V to 0.7 V; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits (VLSI Circuits), 2015 Symposium on

Conference_Location

Kyoto

Print_ISBN

978-4-86348-502-0

Type

conf

DOI

10.1109/VLSIC.2015.7231319

Filename

7231319