A novel low power double edge triggered flip-flop based on clock gated pulse suppression technique

In this paper, a novel low power double edge triggered flip-flop based on clock-gated pulse suppression technique is proposed. Incorporating this proposed technique with double edge triggered flip-flop reduces the power dissipation in the clocking system. The proposed technique suppresses all the redundant pulses of the clock cycle if the input remains unchanged. This technique is implemented using CMOS 90nm technology in Synopsys HSPICE. The proposed design aims at low power and low power-delay-product as compared to the conventional pulse triggered flip-flops.