DocumentCode
738682
Title
Novel High-Efficiency Three-Level Stacked-Neutral-Point-Clamped Grid-Tied Inverter
Author
Yong Wang ; Rui Li
Author_Institution
Dept. of Electr. Eng., Shanghai Jiao Tong Univ., Shanghai, China
Volume
60
Issue
9
fYear
2013
Firstpage
3766
Lastpage
3774
Abstract
In recent years, high photovoltaic array voltage up to 1000 V and transformerless grid-tied inverter have been increasingly researched and applied to elevate the inverter and the dc power collection efficiency. With the same reasons, a three-level neutral point clamped (3L-NPC) inverter featuring low power device voltage stress and low leakage current becomes increasingly attractive. In this paper, the operation and the features of a novel grid-tied 3L-NPC are presented. The proposed topology is a derivative of the three-level stacked neutral point clamped (3L-SNPC) structure. However, compared with the conventional 3L-SNPC and its pulse width modulation (PWM) strategy, the new topology with novel PWM strategy features completely inactive intrinsic body diodes. Furthermore, only two outer power devices are working with switching frequency, while the other four Insulated Gate Bipolar Transistors (IGBTs) are actually with the grid frequency. Therefore, the relatively high switching frequency is selected to reduce the inverter output filter inductance. A hybrid CoolMosfet and IGBT power module configuration is also proposed based on the new PWM strategy. The calculation shows that the total power device losses are reduced. The experimental results are illustrated in this paper to confirm the operation of the proposed topology and controller.
Keywords
MOSFET; PWM invertors; insulated gate bipolar transistors; 3L-NPC inverter; IGBT power module configuration; PWM strategy features; dc power collection efficiency; grid-tied 3L-NPC; high photovoltaic array voltage; high-efficiency three-level stacked-neutral-point-clamped grid-tied inverter; hybrid CoolMosfet; inactive intrinsic body diodes; insulated gate bipolar transistors; inverter output filter inductance; low leakage current; low power device voltage stress; pulse width modulation; switching frequency; three-level stacked neutral point clamped structure; total power device losses; transformerless grid-tied inverter; Insulated gate bipolar transistors; Inverters; Pulse width modulation; Switches; Switching frequency; Topology; Voltage control; Body diodes; PWM strategy; grid tied; hybrid power module; losses; three-level neutral point clamped (3L-NPC) inverter;
fLanguage
English
Journal_Title
Industrial Electronics, IEEE Transactions on
Publisher
ieee
ISSN
0278-0046
Type
jour
DOI
10.1109/TIE.2012.2204712
Filename
6217306
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