Solid-state transient limiter for capacitor bank switching transients

Transient overvoltage and inrush current are two major transient phenomena which occur because of capacitor switching. In addition to power quality degradation, these transients lead to shortening the lifetime of the capacitor and switching device. In order to reduce these transients, a solid-state capacitor switching transient limiter (SSCSTL) is proposed in this study. The proposed SSCSTL has two operation modes: limiting mode and bypass mode. During the capacitor energising, a DC reactor and a varistor suppress inrush current and transient overvoltage, respectively. During the steady-state mode, the DC reactor is bypassed by a thyristor, so the SSCSTL acts as short-circuit and has no considerable effect on the circuit. The thyristor is triggered by using a new simple structure auto-triggering technique in normal condition. The proposed SSCSTL with a very simple structure as well as fast and reliable performance is an efficient solution to assure the capacitor switching without any transient overvoltage and inrush current. A prototype single-phase SSCSTL is simulated by electromagnetic transient program and tested. The simulation and experiment results show that the proposed SSCSTL considerably reduces the inrush current and transient overvoltage during switching of the capacitor.