• DocumentCode
    740003
  • Title

    Unexpected Latch-Up Through CMOS Triple-Well Structures

  • Author

    Stockinger, Michael ; Secareanu, Radu

  • Author_Institution
    Freescale Semicond., Inc., Austin, TX, USA
  • Volume
    15
  • Issue
    3
  • fYear
    2015
  • Firstpage
    272
  • Lastpage
    279
  • Abstract
    Unexpected device interactions between ESD diodes and NMOS clamps in isolated P-well (triple well) have been observed. This can lead to an SCR-like I-V behavior in TLP measurements and poses a latch-up risk. The cause of this interaction is being analyzed using equivalent circuits with parasitic devices and by TCAD simulations.
  • Keywords
    CMOS integrated circuits; electrostatic discharge; integrated circuit reliability; CMOS triple well structures; ESD diodes; NMOS clamps; isolated P-well; unexpected device interactions; unexpected latch-up; Clamps; Earth Observing System; Electric potential; Electrostatic discharges; MOS devices; Resistance; Semiconductor diodes; CMOS; ESD; Latch-Up; TCAD; Triple Well; latch-up (LU); triple well;
  • fLanguage
    English
  • Journal_Title
    Device and Materials Reliability, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1530-4388
  • Type

    jour

  • DOI
    10.1109/TDMR.2015.2466532
  • Filename
    7185348
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=740003