A Second-Order ΔΣ ADC Using Noise-Shaped Two-Step Integrating Quantizer

In this paper, a new second-order discrete-time ΔΣ ADC using a noise-shaped two-step integrating quantizer is presented. The first quantization step (coarse) is utilized with a flash ADC. The second quantization step (fine) is implemented using a noise-shaped integrating quantizer. As a result, both high resolution and first-order noise shaping is achieved. High quantization resolution enhances the modulator stability whereas the extra order of noise-shaping improves the overall performance. The proposed ΔΣ ADC incorporating the noise-shaped two-step integrating quantizer manifests a second-order noise-shaping with a first-order loop filter. To accommodate the large number of quantization levels of the feedback-DAC, a new feedback topology is presented which uses both analog and digital signals. The prototype ADC is implemented in 0.13 μm CMOS and demonstrates peak SNDR of 70.7 dB while consuming 8.1 mW under a 1.2 V supply, with an OSR of 8 at 80 MHz sampling frequency.