DocumentCode
742269
Title
Time-Delayed Converter-Reshuffling: An Efficient and Secure Power Delivery Architecture
Author
Weize Yu ; Kose, Selcuk
Author_Institution
Dept. of Electr. Eng., Univ. of South Florida, Tampa, FL, USA
Volume
7
Issue
3
fYear
2015
Firstpage
73
Lastpage
76
Abstract
In this letter, a time-delayed converter-reshuffling (CoRe) technique is proposed as a countermeasure against machine learning based differential power analysis (DPA) attacks where the attacker can synchronize the sampling frequency with the operating frequency of the device under attack. The proposed time-delayed CoRe technique exploits the distributed nature of multiphase switched capacitor voltage converters where half of the converter stages are delayed to eliminate the risk of having zero power trace entropy (PTE) under machine learning based DPA attacks. A high PTE value is maintained (above 3.2 for a 64-phase time-delayed CoRe technique) regardless of the phase difference between the attacker´s sampling rate and the operating frequency. In addition, the minimum PTE value of the proposed time-delayed CoRe technique is enhanced from zero to ~ 3 by inserting a certain time-delay to half of the converter stages.
Keywords
capacitors; learning (artificial intelligence); power engineering computing; switching convertors; synchronisation; CoRe technique; PTE; machine learning based DPA attacks; machine learning based differential power analysis attacks; multiphase switched capacitor voltage converters; operating frequency; power delivery architecture; power trace entropy; sampling frequency synchronization; time-delayed converter-reshuffling technique; Delay effects; Entropy; Monitoring; Regulators; Switches; Switching frequency; Synchronization; Machine learning-based DPA attacks; multiphase switched capacitor; power trace entropy; time-delayed;
fLanguage
English
Journal_Title
Embedded Systems Letters, IEEE
Publisher
ieee
ISSN
1943-0663
Type
jour
DOI
10.1109/LES.2015.2433175
Filename
7106483
Link To Document