• DocumentCode
    742284
  • Title

    Timing Yield Slack for Timing Yield-Constrained Optimization and Its Application to Statistical Leakage Minimization

  • Author

    Eun Ju Hwang ; Wook Kim ; Young Hwan Kim

  • Author_Institution
    Pohang Univ. of Sci. & Technol., Pohang, South Korea
  • Volume
    21
  • Issue
    10
  • fYear
    2013
  • Firstpage
    1783
  • Lastpage
    1796
  • Abstract
    This paper focuses on statistical optimization and, more specifically, timing yield (TY)-constrained optimization. For cell replacement in timing-constrained optimization, we need an indicator that examines whether or not a timing violation occurs and gives the available timing for a gate. In deterministic optimization, the timing slack is used for this indicator. Although there is an analogous concept of TY slack in statistical optimization, it has not been well utilized. This paper proposes an effective way to use the TY slack for successful statistical optimization. To achieve this, we present an efficient method to calculate the TY slacks of gates and a strategy that uses timing resources for effective statistical optimization. Based on this work, we propose a novel statistical leakage minimization method that uses the TY slack for a gate change metric. The use of TY-based metrics that are appropriate for statistical design ensures that our method has a better optimization performance at a higher speed. Experimental results on ISCAS-85 benchmark circuits show that the leakage minimization method reduces leakage by 25.2% compared to the statistical benchmark method. In addition, our method has a better runtime when the number of gates is high.
  • Keywords
    integrated circuit design; integrated circuit yield; minimisation; statistical analysis; timing circuits; ISCAS-85 benchmark circuits; cell replacement; deterministic optimization; gate change metric; statistical design; statistical leakage minimization; timing resources; timing violation; timing yield slack; timing yield-constrained optimization; Complexity theory; Delay; Logic gates; Optimization; Standards; Process variation; statistical design; statistical leakage minimization; statistical optimization; statistical static timing analysis (SSTA); timing yield slack; timing yield-constrained optimization;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2012.2220792
  • Filename
    6341120