Short Channel Effects on LTPS TFT Degradation

Double-gate (DG) polysilicon thin-film transistors (TFTs) are considered very important for future large area electronics, due to their capability to electrically control TFT characteristics. The scope of this paper is to study how high performance DG polysilicon TFT degradation is affected by shrinking of the channel length. We applied equivalent dc stress in DG TFTs of different top gate length ${L}_{\rm \top}$ , with channel width ${W} = 8 \mu$ m and bottom gate length fixed at ${L}_{\rm \bot} = 4 \mu$ m. Also, to ensure that we only see effects from the top gate operation, the bottom gate bias was kept constant at ${-}$ 3 V, pushing the carriers towards the top interface. Degradation seemed to be much more intense in the longer device, despite the scaling of the stress field. This could be attributed to the larger number of sub-boundaries and grain boundaries as ${L}_{\rm \top}$ increases, causing larger scattering of the carriers towards the top interface and larger grain-boundary state creation. Low frequency noise measurements support the conclusions regarding the proposed degradation mechanisms of DG polysilicon TFTs with shrinking channel length.