Abstract :
The implementation of a 2-digit modulo-3 linear sequential circuit (LSC) is presented, together with its associated state diagram. Two multiple valued logic (MVL) primitives are identified as suitable building blocks for the realisation of the three basic elements required for higher radix (>2) LSC hardware. Specifically, the hybrid MVL combinational U-gate and the MVL sequential JK flipflop sequencer are identified as vehicles for the implementation of modulo-radix scalars, adders and delayers.
Keywords :
sequential circuits; ternary logic; 2-digit modulo-3 linear sequential circuit; JK multiple-valued logic primitives; building blocks; circuit implementation; combinational U-gate; hardware; higher radix linear sequential circuit; hybrid U-gate/JK flipflop; modulo radix adders; modulo radix delayers; modulo-radix scalars; multiple valued logic; sequential JK flipflop sequencer; state diagram; ternary logic;
