Effects of erase source bias on Flash EPROM device reliability

Author

San, K. Tamer ; Kaya, Çetin ; Ma, T.P.

Author_Institution

Dept. of Electr. Eng., Yale Univ., New Haven, CT, USA

Volume

42

Issue

1

fYear

1995

fDate

1/1/1995 12:00:00 AM

Firstpage

150

Lastpage

159

Abstract

This paper is concerned with the effects of the source bias during the erase operation on the reliability of Flash EPROM devices. It will be shown that positive charge in the tunnel oxide, mostly generated by the erase operation, is a major cause of the unintentional charge loss/gain mechanisms that disturb the data content of the memory cell. The effects of the erase source bias are evaluated in the context of the positive oxide charge generation and the resulting enhancement of the gate current that causes the data loss. An optimal source bias during erase, around 2 V for our samples, is shown to cause the least positive oxide charge. A model based on the band-to-band tunneling-induced hole generation in Si and subsequent hole injection during the erase operation is presented and discussed

Keywords

EPROM; MOS memory circuits; elemental semiconductors; integrated circuit reliability; integrated circuit testing; silicon; tunnelling; 2 V; Si; band-to-band tunneling-induced hole generation; charge loss/gain mechanisms; data content; erase source bias; flash EPROM device; positive oxide charge generation; reliability; tunnel oxide; EPROM; Electrodes; Electrons; FETs; Instruments; MOSFET circuits; Microelectronics; Nonvolatile memory; Substrates; Threshold voltage;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.370023

Filename

370023