Si-OEIC with a built-in PIN-photodiode

Author

Yamamoto, Motohiko ; Kubo, Masaru ; Nakao, Kazuhira

Author_Institution

Dept. of Eng., Sharp Corp., Tenri, Japan

Volume

42

Issue

1

fYear

1995

fDate

1/1/1995 12:00:00 AM

Firstpage

58

Lastpage

63

Abstract

A Si-OEIC with a built-in PIN-photodiode has been developed by a new device structure. We have successfully fabricated an optical link receiver with a speed of 50 Mb/s. The new device structure consists of stacked epitaxial layers each with a buried diffusion region. The cutoff frequency of the photodiode thus realized is 300 MHz and the fall time is 1.6 ns. In this paper, the structure of this new device is presented along with its fabrication process, while the performance is analyzed using device simulation. It was found that the speed of the PIN-photodiode in the Si-OEIC is dominated by carrier transit time in the n⁺-buried region. Further investigation was made by device simulation on two advanced structures. The speed of response of PIN-photodiode will be improved to as fast as 1 ns by the current Si technology. By more advanced technology, 0.7 ns will be achieved for the fall time showing the ultimate characteristic of Si-OEIC

Keywords

elemental semiconductors; integrated circuit modelling; integrated optoelectronics; optical receivers; p-i-n photodiodes; silicon; simulation; 0.7 to 1.6 ns; 300 MHz; 50 Mbit/s; Si; Si OEIC; built-in PIN-photodiode; buried diffusion region; carrier transit time; device simulation; fabrication process; n⁺-buried region; optical link receiver; response speed; stacked epitaxial layers; Bipolar integrated circuits; Cutoff frequency; Epitaxial layers; Fabrication; Microcomputers; Optical fiber communication; Optical receivers; Optical signal processing; Photodiodes; Signal processing;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.370035

Filename

370035