Process and design tradeoffs between minimum RC signal propagation delay and interconnect current density and resistance for deep submicrometer ICs

The demand for higher current density in metal interconnects continues to increase to meet the challenges of higher operation frequency and the more complex design requirement of deep submicrometer integrated circuits. However, improvement in the allowable interconnect current density is typically accompanied by higher wire resistance. The tradeoff between wire resistance and allowable current density must be managed to realize the most efficient interconnect system because both wire resistance and allowable current density affect signal propagation delay. This paper studies the impact of allowable current density on signal propagation delay, and demonstrates an approach to balance wire resistance and allowable current density from the perspective of minimizing signal propagation delay.