Effects of layout methods of RFCMOS on noise performance

Author

Wu, Wen ; Lam, Sang ; Chan, Mansun

Author_Institution

Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., China

Volume

52

Issue

12

fYear

2005

Firstpage

2753

Lastpage

2759

Abstract

This paper presents a study on the effects of different layout methods on the noise performance of RF CMOS transistors. The optimization of RF characteristics using multifinger layout and a more compact waffle layout with Manhattan-oriented polysilicon gate are studied. The waffle layout is demonstrated to have a larger design window through the simulation as well as the experimental data. The improvement of both the maximum oscillation frequency f_max and the cutoff frequency f_T at the same biasing condition leads to the improvement on RF noise performance for the waffle MOSFETs. Compared with the multifinger devices, the SpectreRF simulation reveals that 10% reduction in noise figure is achieved when the waffle MOSFETs are used in CMOS low-noise amplifiers.

Keywords

CMOS integrated circuits; MOSFET; integrated circuit layout; semiconductor device models; semiconductor device noise; CMOS low noise amplifiers; Manhattan oriented polysilicon gate; RF CMOS transistor; SpectreRF simulation; compact waffle layout; multifinger layout; noise figure; noise performance; waffle MOSFET; CMOS technology; Capacitance; Circuit noise; Cutoff frequency; Fingers; Low-noise amplifiers; MOSFETs; Microwave devices; Noise figure; Radio frequency; Cutoff frequency; MOSFET; layout; maximum oscillation frequency; noise; radio frequency (RF);

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2005.859694

Filename

1546341