Title :
A new dynamic gate capacitance measurement protocol to evaluate integrated high-voltage devices´ switching loss performances in power management applications
Author :
Grelu, C. ; Baboux, N. ; Bianchi, R.A. ; Plossu, C.
Author_Institution :
LPM, CNRS, Villeurbanne, France
Abstract :
A novel dynamic gate capacitance characterization technique is proposed to evaluate switching losses in power devices. Dynamic gate capacitance is obtained by measuring the gate displacement current due to the application of a controlled gate voltage pulse, closely matching real operation conditions of power switches. Several architectures for 20-V MOSFET transistors, integrated in a low-cost power management 0.13-μm CMOS technology, are studied. Experimental results are compared to a specific small-signal model for switching transition gate capacitance.
Keywords :
CMOS integrated circuits; MOSFET; capacitance measurement; field effect transistor switches; losses; power field effect transistors; power integrated circuits; switching transients; 0.13 micron; 20 V; CMOS; MOSFET; Miller effect; controlled gate voltage pulse; gate capacitance measurement protocol; gate displacement current; high voltage devices; power devices; power management; power switches; small signal model; switching loss; switching transition; CMOS technology; Capacitance measurement; Current measurement; Displacement measurement; Energy management; Performance evaluation; Power measurement; Protocols; Pulse measurements; Switching loss; Miller effect; power losses; switching characterization;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/TED.2005.859659
