DocumentCode :
747556
Title :
Design of a-Si TFT demultiplexers for driving gate lines in active matrix arrays
Author :
Moez, Kambiz K.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Waterloo, Ont., Canada
Volume :
52
Issue :
12
fYear :
2005
Firstpage :
2806
Lastpage :
2809
Abstract :
Two a-Si thin-film transistors (TFTs) demultiplexer circuits, resistive load (RL) and complementary-like logic (CLL), are proposed and compared with the conventional pass transistor logic (PTL) demultiplexer circuit. Analytical and experimental results indicate that the proposed RL and CLL demultiplexers outperform the PTL circuit by providing larger output voltage swings (OVSs), faster dynamic responses, and less OVS sensitivities to the device instability. The pulse-bias stress experiments, simulating the normal condition of operation, are conducted both on individual a-Si TFTs and a-Si TFT demultiplexer circuits, and the variations in device/circuit electrical characteristics are measured during 12 h. The measurement results indicate that the OVS degradation of proposed circuits can be limited to 7 mV/h, suggesting a long circuit lifetime.
Keywords :
amorphous semiconductors; demultiplexing equipment; driver circuits; silicon; thin film transistors; OVS degradation; Si; TFT demultiplexers; active matrix arrays; amorphous semiconductors; circuit lifetime; complementary-like logic; device instability; dynamic responses; electrical characteristics; gate lines; output voltage swings; pass transistor logic; pulse-bias stress experiments; resistive load; thin-film transistors; Circuit analysis; Circuit simulation; Electric variables; Logic circuits; Logic devices; Pulse circuits; Pulse measurements; Stress; Thin film transistors; Voltage; Amorphous semiconductors; demultiplexing; thin-film transistors;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/TED.2005.859709
Filename :
1546348
Link To Document :
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