A 1.5-V 12-bit power-efficient continuous-time third-order ΣΔ modulator

Author

Gerfers, Friedel ; Ortmanns, Maurits ; Manoli, Yiannos

Author_Institution

Inst. of Microsystem Technol., Albert Ludwigs Univ., Freiburg, Germany

Volume

38

Issue

8

fYear

2003

Firstpage

1343

Lastpage

1352

Abstract

This paper presents the design strategy, implementation, and experimental results of a power-efficient third-order low-pass ΣΔ analog-to-digital converter (ADC) using a continuous-time (CT) loop filter. The loop filter has been implemented by using active RC integrators. Several power optimizations, design requirements, and performance limitations relating to circuit nonidealities in the CT modulator are presented. The influence of the low supply voltage on the various building blocks such as the amplifier as well as on the overall ΣΔ modulator is discussed. The ADC was implemented in a 3.3-V 0.5-μm CMOS technology with standard threshold voltages. Measurements of the low-power 1.5-V CT ΣΔ ADC show a dynamic range and peak signal-to-noise-plus-distortion ratio of 80 and 70 dB, respectively, in a bandwidth of 25 kHz. The measured power consumption is only 135 μW from a single 1.5-V power supply.

Keywords

CMOS integrated circuits; continuous time systems; integrating circuits; low-power electronics; sigma-delta modulation; 0.5 micron; 1.5 V; 12 bit; 135 muW; 25 kHz; 3.3 V; CMOS; active RC integrators; analog-to-digital converter; circuit nonidealities; continuous-time loop filter; continuous-time third-order ΣΔ modulator; dynamic range; low supply voltage; peak signal-to-noise-plus-distortion ratio; performance limitations; power consumption; threshold voltages; Analog-digital conversion; Bandwidth; CMOS technology; Circuits; Design optimization; Dynamic range; Filters; Low voltage; Power measurement; Threshold voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2003.814432

Filename

1214727