Algorithmic low power FIR cores

The authors present a number of novel architectures for the implementation of low power FIR filtering cores. These architectures are directly translated from flexible algorithms which exploit data and coefficient correlation in order to minimise the effective switched capacitance on the multiplier, and data/coefficient buses. Another characteristic of these algorithms is that they can be combined to form more power-efficient algorithms which in turn could be mapped to more effective architectures. The paper describes the FIR filtering architectures, the arithmetic processing cores which characterise individual architectures, and provides results which demonstrate up to 39% reduction in power. In addition, the paper provides an analysis of the arithmetic processing cores and the impact of their constituent components on the overall power saving with different algorithms.