Title :
Design and Implementation of Low-Power Hardware Architecture With Single-Cycle Divider for On-Line Clustering Algorithm
Author :
Tse-Wei Chen ; Ikeda, Makoto
Author_Institution :
VLSI Design & Educ. Center (VDEC), Univ. of Tokyo, Tokyo, Japan
Abstract :
A dual-stage hardware architecture that supports two kinds of moving averages for the on-line clustering algorithm is proposed. The architectural design of this work is different from the one of previous works that focus on the iterative clustering algorithm. The system includes a set of memories that operates in ping-pong mode, so that the Manhattan distances can be computed when the centroids are updated. The high-throughput parallel divider in the moving-average engine is a new solution to reduce the computational time of one division operation to a single clock cycle and to calculate cumulative moving averages with no precision loss. Two hardware examples show the robustness of the proposed architecture, and the architectural analysis is performed with the 90 nm CMOS technology. In the first example, the gate count is the smallest and the normalized power consumption of this work is the lowest among previous works. In the second example, the architecture is compared with related works, which implement the Self-Organizing Map (SOM) algorithm. The proposed work has high flexibility for parameter combinations and can achieve high performance for color quantization in a single iteration. The functionalities of the proposed system are also verified with the background subtraction application.
Keywords :
CMOS logic circuits; computer architecture; learning (artificial intelligence); logic design; moving average processes; pattern clustering; self-organising feature maps; Manhattan distances; SOM algorithm; background subtraction application; color quantization; cumulative moving averages; dual-stage hardware architecture; high-throughput parallel divider; iterative clustering algorithm; low-power hardware architecture; moving-average engine; normalized power consumption; online clustering algorithm; ping-pong mode; self-organizing map; size 90 nm; Clustering methods; digital circuits; logic design; machine learning; signal processing;
Journal_Title :
Circuits and Systems I: Regular Papers, IEEE Transactions on
DOI :
10.1109/TCSI.2013.2239098