Title :
Open-loop phase-locking scheme for signal synchronisation
Author :
Yang, Yixin ; Wang, Chunyan
Author_Institution :
Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que., Canada
fDate :
6/26/2003 12:00:00 AM
Abstract :
An open-loop phase-locking scheme is proposed. It uses an open-loop control mode to avoid the problem of weak feedback in a phase-locked loop in the case that the output frequency is much higher than that of the reference. A synchronous circuit is designed with this scheme, and is simulated with the transistor models of a 0.18 μm technology. The phase error is 59.13/14.26 ps peak-to-peak/rms when the frequency of the circuit output is 270 MHz.
Keywords :
CMOS digital integrated circuits; digital phase locked loops; high-speed integrated circuits; synchronisation; 0.18 micron; 270 MHz; PLL; digital open-loop approach; open-loop control mode; open-loop phase-locking scheme; phase error; phase-locked loop; signal synchronisation; synchronous circuit; transistor models;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20030637
